广场舞《我爱你》:谁能帮我翻译这段文字啊?

来源:百度文库 编辑:高校问答 时间:2024/05/06 04:40:10
CPLD(复杂可编程逻辑器件)是PLD 的家族成员之一,它比一般的PLD 具有更高的集成度、良好的工作可靠性和稳定性。它是一种具有高集成度、良好的工作可靠性和稳定性的可编程数字逻辑芯片,因此受到了世界范围内电子工程设计人员的广泛关注和普遍欢迎。用CPLD作频率计数字电路的核心部件,可简化频率计的硬件电路,提高系统的工作速度,节约设计与制造成本。本文是笔者用Verilog HDL 语言、模块化方法设计制作的6位十进制数字频率计系统。

CPLD is one of the family members of PLD, it has higher integrated level , good working dependability and stability than general PLD. It whether one have high integrated level, good working dependability and stability can programme the digital logic chip , so has received extensive concern and popular welcome of the electronic engineering designer in the whole world. Make the key part of the digital circuit of the cymometer with CPLD, can simplify the hardware circuit of the cymometer , improve the working pace of the system, save the design and manufacturing cost . This text is that the author designed and made 6 decimal digit cymometer systems with Verilog HDL language, module method .

CPLD is one of the members of the PLD family. It has higher level of integration, good working reliability and stability than general PLDs. It is programmable digital logic chips with high integrattion levels , good working reliability and stability, so it has received extensive reviews and popular welcome among electronic engineering designers in the whole world. Using CPLD as the key part of the frequency counter digital circuits, it simplifies the hardware circuits of frequency counters, increases the working speed of the system, saves the designing and manufacturing costs. The author of this article designed and produced the six-digit decimal system of digital frequency counters using Verilog HDL language, module method.

最后一句中文看不太懂。抱歉。