3d渲染都是黑的:一个程序 一位十进制全加器 仿真不对呀 真烦呀

library ieee;

use ieee.std_logic_1164.all;

entity adder is

port(a,b,cin:in std_logic;

s,co:out std_logic);

end adder;

architecture full of adder is

signal c,d,e:std_logic;

begin

process(a,b,cin)

begin

c<=a xor b;

d<=a and b;

s<=c xor cin;

e<=c and cin;

co<=e xor d;

end process;

end adder;

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labrary ieee;

use ieee_std_logic_1164.all;

entity add4 is

port(cin:in std_logic;

x,y:in std_logic_vector(3 downto 0);

sum:out std_logic_vector(3 downto 0）；

co：out std_logic);

architecture stru of addr is

compnent adder

port(a,b,cin:in std_logic;

s,co:out_std_logic);

end compnent;

signal z:std_logic_vector(2 downto 0);

begin

u0:adder port map(x(0),y(0),cin,sum(0),z(0));

u1:adder port map(x(1),y(1),z(0),sum(1),z(1));

u2:adder port map(x(2),y(2),z(1),sum(2),z(2));

u3:adder port map(x(3),y(3),z(2),sum(3),co);

end stru;
library ieee;
use ieee.std_logic_1164.all;
use ieee.ste_logic_unsigned.all;
entity adder is
port(cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
co:out std_logic);
end adder;
architecture behav of adder is
signal temp:std_logic_vector(4 downto 0);
begin
process(a,b,cin)
begin
temp<=('0'&a)+b+cin;
if(temp(3 downto 0)>9 or (temp(4)='1')then
s<=temp(3 downto 0)+6;
co<='1';
else
s<=temp(3 downto 0);
co<='0';
end if;
end process;
end behavl;